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cy7c09569v cy7c09579v 3.3 v 16 k / 32 k 36 flex36 ? synchronous dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-06054 rev. *f revised august 23, 2011 features true dual-ported memory cells which allow simultaneous access of the same memory location two flow-through/pipelined devices ? 16 k 36 organization (cy7c09569v) ? 32 k 36 organization (cy7c09579v) 0.25-micron cmos for optimum speed/power three modes ? flow-through ? pipelined ? burst bus-matching capabilities on right port (36 to 18 or 9) byte-select capabilities on left port 100-mhz pipelined operation high-speed clock to data access 5/6 ns 3.3 v low operating power ? active = 250 ma (typical) ? standby = 10 a (typical) fully synchronous interface for ease of use burst counters increment addresses internally ? shorten cycle times ? minimize bus noise ? supported in flow-through and pipelined modes counter address read back via i/o lines single chip enable automatic power-down commercial and industrial temperature ranges compact package ? 144-pin tqfp (20 20 1.4 mm) ? 144-pin pb-free tqfp (20 20 1.4 mm) ? 172-ball bga (1.0-mm pitch) (15 15 0.51 mm) functional description the cy7c09569v and cy7c09579v are high-speed 3.3 v synchronous cmos 16 k and 32 k 36 dual-port static rams. two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. registers on control, address, and data lines allow for minimal set-up and hold times. in pipelined output mode, data is regis- tered for decreased cycle ti me. clock to data valid t cd2 = 5 ns (pipelined). flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. in flow-through mode data will be available t cd1 = 12.5 ns after the address is clocked into the device. pipelined output or flow-through mode is selected via the ft /pipe pin. each port contains a burst counter on the input address register. the internal write pulse width is independent of the external r/w low duration. the internal write pulse is self-timed to allow the shor test possible cycle times. a high on ce for one clock cycle will power down the internal circuitry to reduce the static power consumption. in the pipelined mode, one cycl e is required with ce low to reactivate the outputs. counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. a port?s burst counter is loaded with the port?s address strobe (ads ). when the port?s count enable (cnten ) is asserted, the address counter will in crement on each low-to-high transition of that port?s clock signal. this will read/write one word from/into each successive address location until cnten is deasserted. the counter can address the entire memory array and will loop back to the start. counter reset (cntrst ) is used to reset the burst counter. parts are available in 144-pin thin quad plastic flatpack (tqfp), 144-pin pb-free thin quad plastic flatpack (tqfp) and 172-ball ball grid array (bga) packages. selection guide cy7c09569v cy7c09579v unit ?100 ?83 f max2 (pipelined) 100 83 mhz maximum access time (clock to data, pipelined) 5 6 ns typical operating current i cc 250 240 ma typical standby current for i sb1 (both ports ttl level) 30 25 ma typical standby current for i sb3 (both ports cmos level) 10 10 a cy7c09569v cy7c09579v cy7c09289v cy7c09369v cy7c09379v cy7c09389v3.3 v 16 k / 32 k 36 flex36 ? synchronous dual-port static ram
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 2 of 32 logic block diagram r/w l b 0 ?b 3 oe l ft /pipe l i/o 18l ?i/o 26l a 0 ?a 13/14l clk l ads l cnten l cntrst l a 0 ?a 13/14r clk r ads r cnten r cntrst r counter/ address register decode true dual-ported ram array counter/ address register decode 9 [1] [1] 14/15 14/15 i/o 27l ?i/o 35l 9 i/o 0l ?i/o 8l 9 i/o 9l ?i/o 17l 9 ce l i/o control left port control logic r/w r oe r ft /pipe r 9 9 i/o r 9 9 ce r i/o control right port control logic bus match 9/18/36 bm size be note 1. a 0 ?a 13 for 16k; a 0 ?a 14 for 32 k devices.
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 3 of 32 contents pin configurations ........................................................... 4 pin definitions .................................................................. 6 maximum ratings.............................................................. 7 operating range ............................................................... 7 electrical characteristics ................................................. 7 capacitance ...................................................................... 7 ac test load and waveforms ......................................... 8 switching characteristics ................................................ 9 switching waveforms .................................................... 10 read/write and enable operation.................................. 23 address counter control operation.............................. 23 right port configuration................................................. 24 right port operation ....................................................... 24 readout of internal address counter............................ 24 left port operation ......................................................... 24 counter operation .......................................................... 25 bus match operation ..................................................... 25 ordering information ...................................................... 27 ordering code definitions ..... .................................... 27 package diagrams .......................................................... 28 acronyms ........................................................................ 30 document conventions ................................................. 30 units of measure ....................................................... 30 sales, solutions, and legal information ...................... 32 worldwide sales and design s upport ......... .............. 32 products .................................................................... 32 psoc solutions ......................................................... 32
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 4 of 32 pin configurations 144-pin thin quad flatpack (tqfp) top view i/o32l i/o33r i/o23l i/o33l 2 3 4 i/o34l i/o34r 5 i/o35l i/o35r 6 a0l a0r 7 a1l a1r 8 a2l a2r 9 a3l a3r 10 a4l a4r 11 a5l a5r 12 a6l a6r 13 a7l 108 a7r 14 b0 107 bm 15 b1 106 size 16 b2 105 be 17 b3 104 vss 18 oel 103 oer 19 r/wl 102 r/wr 20 vdd 101 vdd 21 vss 100 vss 22 vss 99 vss 23 cel 98 cer 24 clkl 97 clkr 25 adsl 96 adsr 26 cntrstl 95 cntrstr 27 cntenl 94 cntenr 28 ft /pipel 93 ft /piper 29 a8l 92 a8r 30 a9l 91 a9r 31 a10l 90 a10r 32 a11l 89 a11r 33 a12l 88 a12r 34 a13l 87 a13r 35 nc 86 nc 36 i/o26l 85 i/o26r i/o25l 84 i/o25r i/o24l 83 i/o24r 82 81 41 42 43 44 i/o22l i/o31l 45 vss vss 46 i/o21l i/o30l 47 i/o20l i/o29l 48 i/o19l i/o28l 49 i/o18l i/o27l 50 vdd vdd 51 i/o8l i/o17l 52 i/o7l i/o16l 53 i/o6l i/o15l 54 i/o5l i/o14l 55 vss vss 56 i/o4l i/o13l 57 i/o3l i/o12l 58 i/o2l 143 i/o11l 59 i/o1l 142 i/o10l 60 i/o0l 141 i/o9l 61 i/o0r 140 i/o9r 62 i/o1r 139 i/o10r 63 i/o2r 138 i/o11r 64 i/o3r 137 i/o12r 65 i/o4r 136 i/o13r 66 vss 135 vss 67 i/o5r 134 i/o14r 68 i/o6r 133 i/o15r 69 i/o7r 132 i/o16r 70 i/o8r 131 i/o17r 71 vdd 130 vdd 72 i/o18r 129 i/o27r 123 i/o19r 128 i/o28r 122 i/o20r 127 i/o29r 121 i/o21r 126 i/o30r 120 vss 125 vss 119 i/o22r 124 i/o31r 118 i/o23r i/o32r 117 116 37 38 39 40 80 79 78 77 76 75 74 73 115 114 113 112 111 110 109 144 1 cy7c09569v (16 k 36) cy7c09579v (32 k 36) [2] [3] notes 2. this pin is a14l for cy7c09579v. 3. this pin is a14r for cy7c09579v.
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 5 of 32 172-ball ball grid array (bga) top view 1234567891011121314 a i/o32l i/o30l nc vss i/o13l vdd i/o11l i/o11r vdd i/o13r vss nc i/o30r i/o32r b a0l i/o33l i/o29 i/o17l i/o14l i/o12l i/o9l i/o 9r i/o12r i/o14r i/o17r i/o29r i/o33r a0r c nc a1l i/o31l i/o27l nc i/o15l i/o10l i/o10r i/o15r nc i/o27r i/o31r a1r nc d a2l a3l i/o35l i/o34l i/o28l i/o16l vss vs s i/o16r i/o28r i/o34r i/o35r a3r a2r e a4l a5l nc b0l nc nc nc nc bm nc a5r a4r f vdd a6l a7l b1l nc nc size a7r a6r vdd g oel b2l b3l cel cer vss be oer h vss r/w la8lclkl clkr a8r r/w r vss j a9l a10l vss adsl nc nc adsr vss a10r a9r k a11l a12l nc cntrstl nc nc nc nc cntrstr nc a12r a11r l ft /pipel a13l cntenl i/o26l i/o25l i/o19l vss vss i/o19r i/o25r i/o26r cntenr a13r ft /piper m nc nc [4] i/o22l i/o18l nc i/o7l i/o2l i/o2r i/o7r nc i/o18r i/o22r nc [5] nc n i/o24l i/o20l i/o8l i/o6l i/o5l i/o3l i/o0l i/o 0r i/3r i/o5r i/o6r i/o8r i/o20r i/o24r p i/o23l i/o21l nc vss i/o4l vdd i/o1l i/o1r vdd i/o4r vss nc i/o21r i/o23r notes 4. this pin is a14l for cy7c09579v. 5. this pin is a14r for cy7c09579v.
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 6 of 32 pin definitions left port right port description a 0l ?a 13/14l a 0r ?a 13/14r address inputs (a 0 ?a 13 for 16 k, a 0 ?a 14 for 32 k devices) ads l ads r address strobe input. used as an address qualifier. this signal should be asserted low to assert the part using the externally supplied address on ad dress pins. to load this address into the burst address counter both ads and cnten have to be low. ads is disabled if cntrst is asserted low ce l ce r chip enable input clk l clk r clock signal. this input can be free-running or strobed. maximum clock input rate is f max cnten l cnten r counter enable input. asserting this signal lo w increments the burst address counter of its respective port on each rising edge of clk. cnten is disabled if cntrst is asserted low cntrst l cntrst r counter reset input. asserting this signal low rese ts the burst address counter of its respective port to zero. cntrst is not disabled by asserting ads or cnten i/o 0l ?i/o 35l i/o 0r ?i/o 35r data bus input/output oe l oe r output enable input. this signal must be asserted low to enable the i/o data pins during read operations r/w l r/w r read/write enable input. this signal is asserted lo w to write to the dual port memory array. for read operations, assert this pin high ft /pipe l ft /pipe r flow-through/pipelined select input. for flow-thr ough mode operation, assert this pin low. for pipelined mode operation, assert this pin high b 0l ?b 3l ? byte select inputs. asserting these signals enabl e read and write operations to the corresponding bytes of the memory array ? bm, size select pins for bus matching. see bus matching for details ? be big endian pin. see bus matching for details v ss ground input v dd power input
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 7 of 32 maximum ratings [6] exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature.................................... ?65 c to +150 c ambient temperature with power applied ........ ........... ........... ............ ......?55 c to +125 c supply voltage to ground potential ................... ?0.5 v to +4.6 v dc voltage applied to outputs in high z state..............................?0.5 v to v dd + 0.5 v dc input voltage ....................................?0.5 v to v dd + 0.5 v [7] output current into outputs (low) .................................. 20 ma static discharge voltage............................................... > 2001 v latch-up current ..........................................................> 200 ma operating range range ambient temperature v dd commercial 0 c to +70 c 3.3 v 165 mv electrical characteristics over the operating range parameter description cy7c09569v cy7c09579v unit -100 -83 min typ max min typ max v oh output high voltage (v dd = min., i oh = ?4.0 ma) 2.4 ? ? 2.4 ? ? v v ol output low voltage (v dd = min., i ol = +4.0 ma) ? ? 0.4 ? ? 0.4 v v ih input high voltage 2.0 ? ? 2.0 ? ? v v il input low voltage ? ? 0.8 ? ? 0.8 v i oz output leakage current ?10 ? 10 ?10 ? 10 a i cc operating current (v dd = max., i out = 0 ma) outputs disabled ? 250 385 ? 240 360 ma i sb1 standby current (both ports ttl level) ce l & ce r v ih , f = f max ? 30 75 ? 25 70 ma i sb2 standby current (one port ttl level) ce l | ce r v ih , f = f max ? 170 220 ? 160 210 ma i sb3 standby current (both ports cmos level) ce l & ce r v dd ? 0.2v, f = 0 ?0.01 1 ?0.01 1 ma i sb4 standby current (one port cmos level) ce l | ce r v ih , f = f max ? 150 200 ? 140 190 ma capacitance parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3 v 10 pf c out output capacitance 10 pf notes 6. the voltage on any input or i/o pin can not exceed the power pin during power-up. 7. pulse width < 20 ns.
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 8 of 32 ac test load and waveforms v th = 1.5 v output c (a) normal load (load 1) r = 50 z 0 = 50 [8] 3.0 v v ss 90% 90% 10% 3ns 3 ns 10% all input pulses 3.3 v output c = 5 pf (b) three-state delay (load 2) r2 = 435 r1 = 590 1 2 3 4 5 6 7 30 60 80 100 200 for t cd2 (ns) capacitance (pf) 20 [9] notes 8. external ac test load capacitance = 10 pf. 9. (internal i/o pad capacitance = 10 pf) + ac test load.
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 9 of 32 switching characteristics (over the operating range) parameter description cy7c09569v/cy7c09579v unit ?100 ?83 min max min max f max1 f max flow-through ? 67 ? 45 mhz f max2 f max pipelined ? 100 ? 83 mhz t cyc1 clock cycle time - flow-through 15 ? 22 ? ns t cyc2 clock cycle time - pipelined 10 ? 12 ? ns t ch1 clock high time - flow-through 6.5 ? 7.5 ? ns t cl1 clock low time - flow-through 6.5 ? 7.5 ? ns t ch2 clock high time - pipelined 4 ? 5 ? ns t cl2 clock low time - pipelined 4 ? 5 ? ns t r clock rise time ? 3 ? 3 ns t f clock fall time ? 3 ? 3 ns t sa address set-up time 3.5 ? 4 ? ns t ha address hold time 0.5 ? 0.5 ? ns t sb byte select set-up time 3.5 ? 4 ? ns t hb byte select hold time 0.5 ? 0.5 ? ns t sc chip enable set-up time 3.5 ? 4 ? ns t hc chip enable hold time 0.5 ? 0.5 ? ns t sw r/w set-up time 3.5 ? 4 ? ns t hw r/w hold time 0.5 ? 0.5 ? ns t sd input data set-up time 3.5 ? 4 ? ns t hd input data hold time 0.5 ? 0.5 ? ns t sad ads set-up time 3.5 ? 4 ? ns t had ads hold time 0.5 ? 0.5 ? ns t scn cnten set-up time 3.5 ? 4 ? ns t hcn cnten hold time 0.5 ? 0.5 ? ns t srst cntrst set-up time 3.5 ? 4 ? ns t hrst cntrst hold time 0.5 ? 0.5 ? ns t oe output enable to data valid ? 8 ? 9 ns t olz [10, 11] oe to low z 2 ? 2 ? ns t ohz [10, 11] oe to high z 1 7 1 7 ns t cd1 clock to data valid - flow-through ? 12.5 ? 18 ns t cd2 clock to data valid - pipelined ? 5 ? 6 ns t ca1 clock to counter address valid - flow-through ? 12.5 ? 18 ns t ca2 clock to counter address valid - pipelined ? 9 ? 10 ns t dc data output hold after clock high 2 ? 2 ? ns t ckhz [10, 11] clock high to output high z 2 6 2 7 ns t cklz [10, 11] clock high to output low z 2 ? 2 ? ns port to port delays t cwdd write port clock high to read data delay ? 30 ? 35 ns t ccs clock to clock set-up time ? 9 ? 10 ns notes 10. this parameter is guaranteed by design, but it is not production tested. 11. test conditions used are load 2.
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 10 of 32 switching waveforms read cycle for flow-through output (ft /pipe = v il ) [12, 13, 14, 15] read cycle for pipelined operation (ft /pipe = v ih ) [12, 13, 14, 15] notes 12. oe is asynchronously controlled; all other in puts are synchronous to the rising clock edge. 13. ads = v il , cnten = v il and cntrst = v ih . 14. the output is disabled (high-impedance state) by ce =v ih following the next rising edge of the clock. 15. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. t ch1 t cl1 t cyc1 t sc t hc t dc t ohz t oe t sc t hc t sw t hw t sa t ha t cd1 t ckhz t dc t olz t cklz a n a n+1 a n+2 a n+3 q n q n+1 q n+2 clk ce r/w address data out oe t sb t hb b 0-3 t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency t sb t hb b 0-3
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 11 of 32 bus match read cycle for flow-through output (ft /pipe = v il ) [16, 17, 18, 19, 20] bus match read cycle for pipelined operation (ft /pipe = v ih ) [16, 17, 18, 19, 20] notes 16. oe is asynchronously controlled; all other in puts are synchronous to the rising clock edge. 17. the output is disabled (high-impedance state) by ce =v ih following the next rising edge of the clock. 18. timing shown is for x18 bus matching; x9 bus matc hing is similar with 4 cycles between address inputs. 19. see table ?right port operation? for data output on first and subsequent cycles. 20. cnten = v il . in x9 and x18 bus matching burst mode operations (write or read), ads can toggle on the risi ng edge of every clock cycl e or it can be at v ih level all the time except when loading the initial external address (i.e. ads = v il only required when reading or writing the first byte or word). switching waveforms (continued) t ch1 t cl1 t cyc1 t dc t sc t hc t sw t hw t sa t ha t dc t cklz a n a n a n+1 a n+1 q n q n q n+1 clk ce r/w address data out oe low q n+1 1st cycle 1st cycle 2nd cycle 2nd cycle t cd1 ads t ch2 clk ce r/w address data out oe a n a n a n+1 a n+1 q n q n+1 q n t cyc2 t cl2 t sc t hc t sw t hw t sa t ha 1 latency t cd2 t clkz low 1st cycle 2nd cycle 1st cycle t cd2 t cd2 t dc t dc t dc ads
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 12 of 32 bank select pipelined read [21, 22] left port write to flow-through right port read [22, 23, 24, 25, 26] notes 21. in this depth expansion example, b1 repr esents bank #1 and b2 is bank #2; each b ank consists of one cypress dual-port device from this data sheet. address (b1) = address (b2) . 22. b0 = b1 = b2 = b3 = bm = size = ads = cnten = v il , cntrst = v ih . 23. the same waveforms apply for a right port write to flow-through left port read. 24. ce = b0 = b1 = b2 = b3 = ads = cnten =v il ; cntrst = v ih . 25. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 26. if t ccs maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs >maximum specified, then data is not valid until t ccs + t cd1 (t cwdd does not apply in this case). switching waveforms (continued) q 3 q 1 q 0 q 2 a 0 a 1 a 2 a 3 a 4 a 5 q 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk l address (b1) ce (b1) data out(b2) data out(b1) address (b2) ce (b2) t sa t ha t sw t hw t sd t hd match valid t ccs t sw t hw t dc t cwdd t cd1 match t sa t ha match no match no valid valid t dc t cd1 clk l r/w l address l data inl address r data outr clk r r/w r
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 13 of 32 pipelined read-to-write-to-read (oe = v il ) [27, 28, 29, 30] notes 27. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. 28. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 29. ce = ads = cnten = v il ; cntrst = v ih . 30. during ?no operation,? data in memory at the selected address may be corrupted and should be rewritten to ensure data integr ity. switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 14 of 32 pipelined read-to-write-to-read (oe controlled) [31, 32, 33, 34] notes 31. test conditions used are load 2. 32. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 33. ce = ads = cnten = v il ; cntrst = v ih . 34. during ?no operation,? data in memory at the selected address may be corrupted and should be rewritten to ensure data integr ity. switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 t cklz t cd2 q n q n+4 clk ce r/w address data in data out oe
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 15 of 32 bus match pipelined read-to-write-to-read (oe = v il ) [35, 36, 37, 38, 39, 40, 41] notes 35. test conditions used are load 2. 36. timing shown is for x18 bus matching; x9 bus matc hing is similar with 4 cycles between address inputs. 37. see table ?right port operation? for data output on first and subsequent cycles. 38. cnten = v il . in x9 and x18 bus matching burst mode operations (write or read), ads can toggle on the risi ng edge of every clock cycl e or it can be at v ih level all the time except when loading the initial external address (i.e. ads = v il only required when reading or writing the first byte or word). 39. ce = ads = cnten = v il ; cntrst = v ih . 40. during ?no operation,? data in memory at the selected address may be corrupted and should be rewritten to ensure data integr ity. 41. bm, size, and be must be reconfigured 1 cycle before operation is guaranteed. bm, size, and be should remain static for any particular port configuration. switching waveforms (continued) clk ce r/w address data in data out a n a n a n+1 a n+1 a n+2 a n+2 a n+3 a n+3 a n+4 a n+4 q n q n q n+3 q n+3 d n+2 d n+2 1st word 2nd word 1st word 2nd word 1st word 2nd word t ch2 t cyc2 t cl2 t sc t hc t sw t hw t sa t ha read read read read read read no operation 1st cycle 2nd cycle 1st cycle 2nd cycle write write 1st cycle 2nd cycle t cd2 t cd2 t ckhz t cklz t cd2 t dc t sd t hd ads
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 16 of 32 flow-through read-to-write-to-read (oe = v il ) [42, 43, 44, 45, 46, 47] flow-through read-to-write-to-read (oe controlled) [42 , 43, 46, 47, 48] notes 42. ads = v il , cnten = v il and cntrst = v ih . 43. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk. numbers are for reference only. 44. timing shown is for x18 bus matching; x9 bus matc hing is similar with 4 cycles between address inputs. 45. see table ?right port operation? for data output on first and subsequent cycles. 46. ce = ads = cnten = v il ; cntrst = v ih . 47. during ?no operation,? data in memory at the selected address may be corrupted and should be rewritten to ensure data integr ity. 48. output state (high, low, or high-impedance) is determined by the previous cycle control signals. switching waveforms (continued) t ch1 t cl1 t cyc1 t sw t hw t sa t ha t sw t hw t sd t hd a n a n+1 a n+2 a n+2 a n+3 a n+4 d n+2 q n q n+1 q n+3 t cd1 t cd1 t dc t ckhz t cd1 t cd1 t cklz t dc read no operation write read clk ce address r/w data in data out q n t ch1 t cl1 t cyc1 t sw t hw t sa t ha t cd1 t dc t ohz read a n a n+1 a n+2 a n+3 a n+4 a n+5 d n+2 d n+3 t sw t hw t sd t hd t cd1 t cd1 t cklz t dc q n+4 t oe write read clk ce address r/w data in data out oe
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 17 of 32 bus match flow-through read-to-write-to-read (oe = v il ) [49, 50, 51, 52, 53, 54, 55] notes 49. test conditions used are load 2. 50. timing shown is for x18 bus matching; x9 bus matc hing is similar with 4 cycles between address inputs. 51. see table ?right port operation? for data output on first and subsequent cycles. 52. cnten = v il . in x9 and x18 bus matching burst mode operations (write or read), ads can toggle on the risi ng edge of every clock cycl e or it can be at v ih level all the time except when loading the initial external address (i.e. ads = v il only required when reading or writing the first byte or word). 53. ce = ads = cnten = v il ; cntrst = v ih . 54. during ?no operation,? data in memory at the selected address may be corrupted and should be rewritten to ensure data integr ity. 55. bm, size, and be must be reconfigured 1 cycle before operation is guaranteed. bm, size, and be should remain static for any particular port configuration. switching waveforms (continued) clk ce r/w address a n a n a n+1 a n+1 a n+1 a n+1 a n+1 a n+2 data out data in q n q n q n+1 q n+1 d n+1 d n+1 t ch1 t cl1 t cyc1 t hc t sc t hw t sw t ha t sa t hw t sw 1st word 2nd word t hd t sd 1st word 2nd word 1st cycle 2nd cycle 1st cycle 2nd cycle 1st cycle 2nd cycle read read write write read read no operation t cd1 t cd1 t dc t ckhz t cd1 t cd1 t cklz t dc ads
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 18 of 32 pipelined read with address counter advance [56] flow-through read with address counter advance [56] note 56. ce = oe = v il ; r/w = cntrst = v ih . switching waveforms (continued) counter hold read with counter t sa t ha t sad t had t scn t hcn t ch2 t cl2 t cyc2 t sad t had t scn t hcn q x?1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address clk address ads data out cnten a n t dc t ch1 t cl1 t cyc1 t sa t ha t sad t had t scn t hcn q x q n q n+1 q n+2 a n t sad t had t dc t cd1 counter hold read with counter read external address clk address ads data out cnten q n+4 t scn t hcn t cd1 q n+3 t dc read with counter t cd1
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 19 of 32 write with address counter advance (flow-through or pipelined outputs) [57, 58] notes 57. ce = b0 = b1 = b2 = b3 = r/w = v il ; cntrst = v ih . 58. the ?internal address? is equal to the ?external address? when ads = cnten = v il and cntrst =v ih . switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal cnten ads data in address t sa t ha
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 20 of 32 counter reset (pipelined outputs) [59, 60, 61, 62, 63] notes 59. test conditions used are load 2. 60. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 61. ce = b0 = b1 = b2 = b3 = v il . 62. no dead cycle exists durin g counter reset. a read or write cycle ma y be coincidental wit h the counter reset. 63. output state (high, low, or high- impedance) is determined by the previo us cycle control signals. ideally, data out should be in the high-impedance state during a valid write cycle. switching waveforms (continued) clk address internal cnten ads data in address cntrst r/w data out a n a m a p a x 0 1 a n a m a p q 1 q n q 0 d 0 t ch2 t cl2 t cyc2 t sa t ha t sw t hw t srst t hrst t sd t hd t cd2 t cd2 t cklz [63] reset address 0 counter write read address 0 address 1 read read address a n address a m read
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 21 of 32 counter reset (flow-through outputs) [64, 65, 66, 67, 68] notes 64. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 65. during ?no operation,? data in memory at the selected address may be corrupted and should be rewritten to ensure data integr ity. 66. ce = b0 = b1 = b2 = b3 = v il . 67. no dead cycle exists durin g counter reset. a read or write cycle ma y be coincidental wit h the counter reset. 68. output state (high, low, or high- impedance) is determined by the previo us cycle control signals. ideally, data out should be in the high-impedance state during a valid write cycle. switching waveforms (continued) t ch2 t cl2 t cyc2 clk address internal cnten ads data in address cntrst r/w data out q 0 q 1 d 0 a x 0 1 a n a n+1 t srst t hrst t sd t hd t sw t hw a n a n+1 t sa t ha counter reset write address 0 read address 0 read address 1 read address n q n t cd1
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 22 of 32 pipelined read of state of address counter [69, 70, 71] flow-through read of state of address counter [69, 70, 72] notes 69. ce = oe = v il ; r/w = cntrst = v ih . 70. when reading address out in x9 bus match mode, readout of a n is extended by 1 cycle. 71. for pipelined address counter read, signals from address counter operation table from must be valid for 2 consecutive cycles for x36 and x18 mode and for 3 consecutive cycles for x9 mode. 72. for flow-through address counter read, signals from address counter operation table must be valid for consecutive cycles for x36. switching waveforms (continued) cnten clk t ch2 t cl2 t cyc2 address ads a n q x-2 q x-1 q n a n q n+1 q n+2 t sa t ha t sad t had t scn t hcn t scn t hcn t scn t hcn t sad t had load address external counter hold read with counter t ca2 internal address a n+1 a n+2 a n read with counter t dc read counter address data out cnten clk t ch1 t cl1 address ads a n q x q n a n q n+1 q n+2 t sa t ha t sad t had t scn t hcn t scn t hcn t scn t hcn t sad t had load external t cyc1 address counter hold read with counter q n+3 t dc t ca1 internal address a n a n+1 a n+2 a n+3 data out read counter address read with counter
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 23 of 32 read/write and enable operation [73, 74, 75] inputs outputs operation oe clk ce r/w i/o 0 ? i/o 35 x h x high z deselected [76] x l l d in write l l h d out read [76] h x l x high z outputs disabled address counter c ontrol operation [73, 77] address previous address clk oe r/w ads cnten cntrst mode operation x x x x x x l reset counter reset a n x x x l l h load address load into counter a n a n l h l h h hold + read external address blocked - counter address readout x a n x x h h h hold external address blocked - counter disabled x a n x x h l h increment counter increment notes 73. ?x? = ?don?t care,? ?h? = v ih , ?l? = v il . 74. ads , cnten , cntrst = ?don?t care.? 75. oe is an asynchronous input signal. 76. when ce changes state in the pipelined mode, deselection and read happen in the following clock cycle. 77. counter operation is independent of ce .
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 24 of 32 right port configuration [78, 79] right port operation [80] readout of internal address counter [81] bm size configuration i/o pins used 00 x36 i/o 0r?35r 10 x18 i/o 0r?17r 1 1 x9 i/o 0r?8r configuration be data on 1st cycle data on 2nd cycle data on 3rd cycle data on 4th cycle x18 0 dq 0r?17r dq 18r?35r ?? x18 1 dq 18r?35r dq 0r?17r ?? x9 0 dq 0r?8r dq 9r?17r dq 18r?26r dq 27r?35r x9 1 dq 27r?35r dq 18r?26r dq 9r?17r dq 0r?8r configuration address on 1st cycle i/o pins used on 1st cycle address on 2nd cycle i/o pins used on 2nd cycle left port x36 a 0l?14l i/o 3l?17l ?? right port x36 a 0r?14r i/o 3r?17r ?? right port x18 wa, a 0r?14r i/o 2r?17r ?? right port x9 a 6r?14r i/o 0r?8r ba, wa, a 0r?5r i/o 1r?8r left port operation control pin effect b0 i/o 0?8 byte control b1 i/o 9?17 byte control b2 i/o 18?26 byte control b3 i/o 27?35 byte control notes 78. bm, size, and be must be reconfigured 1 cycle before operation is guar anteed. bm, size, and be shoul d remain static for any particular port configuration. 79. in x36 mode, be input is a ?don?t care.? 80. dq represents data output of the chip. 81. x18 and x9 configuration apply to right port only.
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 25 of 32 counter operation the cy7c09569v/09579v dual-port ram (dpram) contains on-chip address counters (one for each port) for the synchronous members of the product family. besides the main x36 format, the right port allows bus matching (x18 or x9, user-selectable). an internal sub-counter provides the extra addresses required to sequence out the 36-bit word in 18-bit or 9-bit increments. the sub-counter counts up in the ?little endian? mode, and counts down if the user has chosen the ?big endian? mode. the address counter is required to be in increment mode in order for the sub-counter to sequence out the second word (in x18 mode) or the remaining three bytes (in x9 mode). for a x36 format (the only active format on the left port), each address counter in the cy7c09579v uses addresses (a 0?14 ). for the right port (allowing fo r the bus-matching feature), a maximum of two address bits (out of a 2-bit sub-counter) are added. 1. ads l/r (pin #23/86) is a port?s address strobe, allowing the loading of that port's burst counters if the corresponding cnten l/r pin is active as well. 2. cnten l/r (pin #25/84) is a port?s count enable, provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applicat ions; when asserted, the address counter will increment on each positive transition of that port's clock signal. 3. cntrst l/r (pin #24/85) is a port's burst counter reset. a new read-back (hold+read mode) feature has been added, which is different between the left and right port due to the bus matching feature provided only for the right port. in read-back mode the internal address of the counter will be read from the data i/os as shown in figure 1 . bus match operation the right port of the cy7c09569v/09579v 16k/32kx36 dual-port sram can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data i/o. the data lines are divided into four lanes, each consisting of 9 bits (byte-size data lines). the bus match select (bm) pin works with bus size select (size) and big endian select (be) to select the bus width (long-word, word, or byte) and data sequencing arrangement for the right port of the dual-port device. a logic ?0? applied to both the bus match select (bm) pin and to the bus size select (size) pin will select long-word (36-bit) operation. a logic ?1? level applied to the bus match select (bm) pin will enable whether byte or word bus width operation on the right port i/os depending on the logic level applied to the size pin. the level of bus match select (bm) must be static throughout normal device operation. the bus size select (size) pin selects either a byte or word data arrangement on the right port when the bus match select (bm) pin is high. a logic ?1? on the size pin when the bm pin is high selects a byte bus (9-bit) data arrangement. a logic ?0? on the size pin when the bm pin is high selects a word bus (18-bit) data arrangement. the level of the bus size select (size) must also be static th roughout normal device operation. the big endian select (be) pin is a multiple-function pin during word or byte bus selection (bm = 1). be is used in big endian select mode to determine the order by which bytes (or words) of data are transferred through the right data port. a logic ?0? on the be pin will select little endian data sequencing arrangement and a logic ?1? on the be pin will select a big endian data sequencing arrangement. under these circum- stances, the level on the be pin should be static throughout dual-port operation. long-word (36-bit) operation bus match select (bm) and bus si ze select (size) set to a logic ?0? will enable standard cycle long-word (36-bit) operation. in this mode, the ri ght port?s i/o operates essentially in an identical fashion to the left port of the dual-port sram. however no byte select control is available. all 36 bits of the long-word are shifted into and out of the right port?s i/o buffer stages. all read and write timing parameters may be identical with respect to the two data ports. when the right port is configured for a long-word size, big- endian select (be) pin has no application and their inputs are ?don?t care? [82] for the external user. address ads cntrst cnten cy7c09569v cy7c09579v ram array counter i/o ? s ___________ _ _____________ _ ______ _ address read-back figure 1. counter operation diagram 9 / be cy7c09569v cy7c09579v 16k/32kx36 dual port bm size 9 / 9 / 9 / x9, x18, x36 / bus mode x36 / figure 2. bus match operation diagram note 82. even though a logic level applied to a ?don?t care? input will not change the logical operation of the dual-port, inputs tha t are temporarily a ?don?t care? (along with unused inputs) must not be allowed to float. they must be forced either high or low.
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 26 of 32 word (18-bit) operation word (18-bit) bus sizing operation is enabled when bus match select (bm) is set to a logic ?1 ? and the bus size select (size) pin is set to a logic ?0.? in this mode, 18 bits of data are ported through i/o 0r?17r . the level applied to the big endian (be) pin determines the right port data i/o sequencing order (big endian or little endian). during word (18-bit) bus size operation, a logic low applied to the be pin will select little endian operation. in this case, the least significant data word is read from the right port first or written to the right port first. a logic ?1? on the be pin during word (18-bit) bus size operation will select big endian operation resulting in the most significant data word being transferred through the right port first. internally, the data will be stored in the appropriate 36-bit lsb or msb i/o memory location. device operation requires a minimum of tw o clock cycles to read or write during word (18-bit) bus size o peration. an internal sub-counter automatically increments the right port multiplexer control when little or big endian operation is in effect. byte (9-bit) operation byte (9-bit) bus sizing operation is enabled when bus match select (bm) is set to a logic ?1? and the bus size select (size) pin is set to a logic ?1.? in this mode, 9 bits of data are ported through i/o 0r?8r . big endian and little endian data sequencing is available for dual-port operation. the level applied to the big endian pin (be) under these circumstances will de termine the right port data i/o sequencing order (big or little endian). a logic low applied to the be pin during byte (9-bit) bus size operation will select little endian operation. in this case, the least significant data byte is read from the right port first or wri tten to the right port first. a logic ?1? on the be pin during byte (9-bit) bus size operation will select big endian operation resulting in the most significant data word to be transferred through the right port first. internally, the data will be stored in the appropriate 36-bit lsb or msb i/o memory location. device operation requires a minimum of four clock cycles to read or write during byte (9-bit) bus size operation. an internal sub-counter automatica lly increments the right port multiplexer control when little or big endian operation is in effect. when transferring data in byte (9-bit) bus match format, the unused i/o pins (i/o 9rq?35r ) are three-stated.
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 27 of 32 ordering information ordering code definitions 16 k 36 3.3 v synchronous dual-port sram speed (mhz) ordering code package name package type operating range 100 cy7c09569v-100axc a144 144-pin pb-free thin quad flat pack commercial CY7C09569V-100BBC bb172 172-ball ball grid array (bga) 32k 36 3.3 v synchronous dual-port sram speed (mhz) ordering code package name package type operating range 100 cy7c09579v-100ac a144 144-pin thin quad flat pack commercial cy7c09579v-100axc a144 144-pin pb-free thin quad flat pack cy7c09579v-100bbc bb172 172-ball ball grid array (bga) 83 cy7c09579v-83ac a144 144-pin thin quad flat pack commercial cy7c09579v-83axc a144 144-pin pb-free thin quad flat pack cy7c09579v-83bbc bb172 172-ball ball grid array (bga) temperature range: c = commercial x = pb-free (rohs compliant) package type: x = a or bb a = 144-pin tqfp bb = 172-ball bga speed grade: xxx = 83 mhz or 100 mhz v = 3.3 v x9 = depth: x = 6 or 7 6 = 16k; 7 = 32k 5 = width: 36 09 = sync 7c = dual port sram cy = cypress device 7c cy 09 5 - xxx x x x x9 v
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 28 of 32 package diagrams figure 3. 144-pin tqfp (20 20 1.4 mm) 51-85047 *d
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 29 of 32 figure 4. 172-ball fbga (15 15 1.25 mm) 51-85114 *c
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 30 of 32 acronyms document conventions units of measure acronym description bga ball grid array cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory tqfp thin quad plastic flatpack tsop thin small outline package we write enable symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes pf pico farad c degree celsius wwatts
cy7c09569v cy7c09579v document number: 38-06054 rev. *f page 31 of 32 document history page document title: cy7c09569v/cy7c09579v 3.3 v 16 k / 32 k 36 flex36 ? synchronous dual-port static ram document number: 38-06054 revision ecn orig. of change submission date description of change ** 110213 szv 12/16/01 change from sp ec number: 38-00743 to 38-06054 *a 122304 rbi 12/27/02 power up requirements added to maximum ratings information *b 349775 ruy see ecn added pb-free information *c 2897215 rame 03/22/10 removed inactive part s from ordering information. updated package diagrams. *d 3110406 admu 12/14/10 added ordering code definitions . minor edits and updated in new template. *e 3162642 admu 02/04/11 removed speed bin -67 added acronyms and document conventions. *f 3352391 admu 08/23/11 no technical updates. updated package diagram spec 51-85047 to *d revision.
document number: 38-06054 rev. *f revised august 23, 2011 page 32 of 32 flex36 is a registered trademark of cypress semiconductor corporation. all other products and company names mentioned in this d ocument may be the trademarks of their respective holders. cy7c09569v cy7c09579v ? cypress semiconductor corporation, 2001-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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